/*
 * X1000 cpm definitions
 *
 * Copyright (c) 2013 Ingenic Semiconductor Co.,Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __X1000_DRAM_H__
#define __X1000_DRAM_H__

/*
 * DDR
 */
#define DDRC_STATUS				0x0 /* DDR Status Register */
#define DDRC_CFG				0x4 /* DDR Configure Register */
#define DDRC_CTRL				0x8 /* DDR Control Register */
#define DDRC_REFCNT				0x18 /* DDR  Auto-Refresh Counter */
#define DDRC_MMAP0				0x24 /* DDR Memory Map Config Register */
#define DDRC_MMAP1				0x28 /* DDR Memory Map Config Register */

#define DDRC_TIMING(n)			(0x60 + 4 * (n - 1)) /* DDR Timing Config Register 1-5 */
#define DDRC_REMAP(n)			(0x9c + 4 * (n - 1)) /* DDR Address Remapping Register 1-5 */

#define DDRC_AUTOSR_EN			0x304

/*
 * DDR APB
 */
#define DDR_APB_OFFSET			(-0x4e0000 + 0x2000)

#define DDRC_PHYRST_CFG			(DDR_APB_OFFSET + 0x80)

/*
 * DDR PHY
 */
#define DDR_PHY_OFFSET			(-0x4e0000 + 0x1000)

#define DDRP_PIR				(DDR_PHY_OFFSET + 0x4) /* PHY Initialization Register */
#define DDRP_PGCR				(DDR_PHY_OFFSET + 0x8) /* PHY General Configuration Register*/
#define DDRP_PGSR				(DDR_PHY_OFFSET + 0xc) /* PHY General Status Register*/

#define DDRP_DLLGCR				(DDR_PHY_OFFSET + 0x10) /* DLL General Control Register*/
#define DDRP_ACDLLCR			(DDR_PHY_OFFSET + 0x14) /* AC DLL Control Register*/

#define DDRP_PTR0				(DDR_PHY_OFFSET + 0x18) /* PHY Timing Register 0 */
#define DDRP_PTR1				(DDR_PHY_OFFSET + 0x1c) /* PHY Timing Register 1 */
#define DDRP_PTR2				(DDR_PHY_OFFSET + 0x20) /* PHY Timing Register 2 */

#define DDRP_ACIOCR				(DDR_PHY_OFFSET + 0x24) /* AC I/O Configuration Register */
#define DDRP_DXCCR				(DDR_PHY_OFFSET + 0x28) /* DATX8 Common Configuration Register */
#define DDRP_DSGCR				(DDR_PHY_OFFSET + 0x2c) /* DDR System General Configuration Register */
#define DDRP_DCR				(DDR_PHY_OFFSET + 0x30) /* DRAM Configuration Register*/

#define DDRP_DTPR0				(DDR_PHY_OFFSET + 0x34) /* DRAM Timing Parameters Register 0 */
#define DDRP_DTPR1				(DDR_PHY_OFFSET + 0x38) /* DRAM Timing Parameters Register 1 */
#define DDRP_DTPR2				(DDR_PHY_OFFSET + 0x3c) /* DRAM Timing Parameters Register 2 */
#define DDRP_MR0				(DDR_PHY_OFFSET + 0x40) /* Mode Register 0 */
#define DDRP_MR1				(DDR_PHY_OFFSET + 0x44) /* Mode Register 1 */
#define DDRP_MR2				(DDR_PHY_OFFSET + 0x48) /* Mode Register 2 */
#define DDRP_MR3				(DDR_PHY_OFFSET + 0x4c) /* Mode Register 3 */

#define DDRP_DTAR				(DDR_PHY_OFFSET + 0x54) /* Data Training Address Register */

#define DDRP_DXGCR(n)			(DDR_PHY_OFFSET + 0x1c0 + n * 0x40) /* DATX8 n General Configuration Register */

/* DDRC Status Register */
#define DDRC_STATUS_ENDIAN		(1 << 7) /* 0 Little data endian
					    1 Big data endian */
#define DDRC_STATUS_MISS		(1 << 6) /* 0 No operation miss DDRC memory mapping
					    1 At least one operation miss DDRC memory mapping */
#define DDRC_STATUS_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
					    1 DDR memory is in deep-power-down state */
#define DDRC_STATUS_PDN			(1 << 4) /* 0 DDR memory is NOT in power-down state
					    1 DDR memory is in power-down state */
#define DDRC_STATUS_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
					    1 DDR memory is in auto-refresh state */
#define DDRC_STATUS_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
					    1 DDR memory is in self-refresh state */
#define DDRC_STATUS_CKE1		(1 << 1) /* 0 CKE1 Pin is low
					    1 CKE1 Pin is high */
#define DDRC_STATUS_CKE0		(1 << 0) /* 0 CKE0 Pin is low
					    1 CKE0 Pin is high */

/* DDRC Configure Register */
#define DDRC_CFG_ROW1_BIT		27 /* Row Address width. */
#define DDRC_CFG_ROW1_MASK		(0x7 << DDRC_CFG_ROW1_BIT)
#define DDRC_CFG_COL1_BIT		24 /* Row Address width. */
#define DDRC_CFG_COL1_MASK		(0x7 << DDRC_CFG_COL1_BIT)
#define DDRC_CFG_BA1			(1 << 23)
#define DDRC_CFG_IMBA			(1 << 22)
#define DDRC_CFG_BL_8			(1 << 21)

#define DDRC_CFG_TYPE_BIT		17
#define DDRC_CFG_TYPE_MASK		(0x7 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR1		(2 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_MDDR		(3 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR2		(4 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR3		(6 << DDRC_CFG_TYPE_BIT)

#define DDRC_CFG_ODT_EN			(1 << 16)  /* ODT EN */

#define DDRC_CFG_MPRT			(1 << 15)  /* mem protect */

#define DDRC_CFG_ROW_BIT		11 /* Row Address width. */
#define DDRC_CFG_ROW_MASK		(0x7 << DDRC_CFG_ROW_BIT)
#define DDRC_CFG_ROW_12			(0 << DDRC_CFG_ROW_BIT) /* 12-bit row address is used */
#define DDRC_CFG_ROW_13			(1 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
#define DDRC_CFG_ROW_14			(2 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */

#define DDRC_CFG_COL_BIT		8 /* Column Address width.
						Specify the Column address width of external DDR. */
#define DDRC_CFG_COL_MASK		(0x7 << DDRC_CFG_COL_BIT)
#define DDRC_CFG_COL_8			(0 << DDRC_CFG_COL_BIT) /* 8-bit Column address is used */
#define DDRC_CFG_COL_9			(1 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
#define DDRC_CFG_COL_10			(2 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
#define DDRC_CFG_COL_11			(3 << DDRC_CFG_COL_BIT) /* 11-bit Column address is used */

#define DDRC_CFG_CS1EN			(1 << 7) /* 0 DDR Pin CS1 un-used
					    1 There're DDR memory connected to CS1 */
#define DDRC_CFG_CS0EN			(1 << 6) /* 0 DDR Pin CS0 un-used
					    1 There're DDR memory connected to CS0 */

#define DDRC_CFG_BA				(1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
					    1 8 bank device, Pin ba[2:0] valid*/
#define DDRC_CFG_DW				(1 << 0) /*0 External memory data width is 16-bit
						1 External memory data width is 32-bit */

/* DDRC Control Register */
#define DDRC_CTRL_DFI_RST		(1 << 23)
#define DDRC_CTRL_DLL_RST		(1 << 22)
#define DDRC_CTRL_CTL_RST		(1 << 21)
#define DDRC_CTRL_CFG_RST		(1 << 20)
#define DDRC_CTRL_ACTPD			(1 << 15) /* 0 Precharge all banks before entering power-down
					     1 Do not precharge banks before entering power-down */
#define DDRC_CTRL_PDT_BIT		12 /* Power-Down Timer */
#define DDRC_CTRL_PDT_MASK		(0x7 << DDRC_CTRL_PDT_BIT)
#define DDRC_CTRL_PDT_DIS		(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
#define DDRC_CTRL_PDT_8			(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
#define DDRC_CTRL_PDT_16		(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
#define DDRC_CTRL_PDT_32		(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
#define DDRC_CTRL_PDT_64		(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
#define DDRC_CTRL_PDT_128		(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */

#define DDRC_CTRL_DPD			(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */

#define DDRC_CTRL_SR			(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
					    0 Drive external DDR device exiting self-refresh mode */
#define DDRC_CTRL_ALH			(1 << 3) /* Advanced Latency Hiding:
					    0 Disable ALH
					    1 Enable ALH */
#define DDRC_CTRL_RDC			(1 << 2) /* 0 dclk clock frequency is lower than 60MHz
					    1 dclk clock frequency is higher than 60MHz */
#define DDRC_CTRL_CKE			(1 << 1) /* 0 Not set CKE Pin High
					    1 Set CKE Pin HIGH */
#define DDRC_CTRL_RESET			(1 << 0) /* 0 End resetting ddrc_controller
					    1 Resetting ddrc_controller */

/* DDRP PHY Initialization Register */
#define DDRP_PIR_INIT			(1 << 0)
#define DDRP_PIR_DLLSRST		(1 << 1)
#define DDRP_PIR_DLLLOCK		(1 << 2)
#define DDRP_PIR_ZCAL			(1 << 3)
#define DDRP_PIR_ITMSRST		(1 << 4)
#define DDRP_PIR_DRAMRST		(1 << 5)
#define DDRP_PIR_DRAMINT		(1 << 6)
#define DDRP_PIR_QSTRN			(1 << 7)
#define DDRP_PIR_EYETRN			(1 << 8)
#define DDRP_PIR_DLLBYP			(1 << 17)
#define DDRP_PIR_LOCKBYP		(1 << 29)

/* DDRP PHY General Status Register */
#define DDRP_PGSR_IDONE			(1 << 0)
#define DDRP_PGSR_DLDONE		(1 << 1)
#define DDRP_PGSR_ZCDONE		(1 << 2)
#define DDRP_PGSR_DIDONE		(1 << 3)
#define DDRP_PGSR_DTDONE		(1 << 4)
#define DDRP_PGSR_DTERR			(1 << 5)
#define DDRP_PGSR_DTIERR		(1 << 6)
#define DDRP_PGSR_DFTEERR		(1 << 7)

/* DDRP DRAM Configuration Register */
#define DDRP_DCR_TYPE_BIT		0
#define DDRP_DCR_TYPE_MASK		(0x7 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_MDDR		(0 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR		(1 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR2		(2 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR3		(3 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_LPDDR2	(4 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_DDR8BNK_BIT	3
#define DDRP_DCR_DDR8BNK_MASK	(1 << DDRP_DCR_DDR8BNK_BIT)
#define DDRP_DCR_DDR8BNK		(1 << DDRP_DCR_DDR8BNK_BIT)
#define DDRP_DCR_DDR8BNK_DIS	(0 << DDRP_DCR_DDR8BNK_BIT)

#endif /* __X1000_DRAM_H__ */
